
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:59:43 06/07/2010
-- Design Name:   processeur
-- Module Name:   /nfs/ensibull/telesun/lelubrec/TESTPUT/tbproc.vhd
-- Project Name:  TESTPUT
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: processeur
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tbproc_vhd IS
END tbproc_vhd;

ARCHITECTURE behavior OF tbproc_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT processeur
	PORT(
		CLK : IN std_logic;
		RESET : IN std_logic;
		DPROG : IN std_logic_vector(15 downto 0);
		DDATAIN : IN std_logic_vector(15 downto 0);
		PIN : IN std_logic_vector(3 downto 0);          
		ADPROG : OUT std_logic_vector(15 downto 0);
		ADDATA : OUT std_logic_vector(15 downto 0);
		DDATAOUT : OUT std_logic_vector(15 downto 0);
		WE : OUT std_logic;
		CE : OUT std_logic;
		OE : OUT std_logic;
		POUT : OUT std_logic_vector(7 downto 0);
		IR : OUT std_logic_vector(15 downto 0);
		ERd : OUT std_logic;
		EPC : OUT std_logic;
		LDPC : OUT std_logic;
		sPC : OUT std_logic_vector(15 downto 0);
		SUAL : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL CLK :  std_logic := '0';
	SIGNAL RESET :  std_logic := '0';
	SIGNAL DPROG :  std_logic_vector(15 downto 0) := (others=>'0');
	SIGNAL DDATAIN :  std_logic_vector(15 downto 0) := (others=>'0');
	SIGNAL PIN :  std_logic_vector(3 downto 0) := (others=>'0');

	--Outputs
	SIGNAL ADPROG :  std_logic_vector(15 downto 0);
	SIGNAL ADDATA :  std_logic_vector(15 downto 0);
	SIGNAL DDATAOUT :  std_logic_vector(15 downto 0);
	SIGNAL WE :  std_logic;
	SIGNAL CE :  std_logic;
	SIGNAL OE :  std_logic;
	SIGNAL POUT :  std_logic_vector(7 downto 0);
	SIGNAL IR :  std_logic_vector(15 downto 0);
	SIGNAL ERd :  std_logic;
	SIGNAL EPC :  std_logic;
	SIGNAL LDPC :  std_logic;
	SIGNAL sPC :  std_logic_vector(15 downto 0);
	SIGNAL SUAL :  std_logic_vector(15 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: processeur PORT MAP(
		CLK => CLK,
		RESET => RESET,
		ADPROG => ADPROG,
		DPROG => DPROG,
		ADDATA => ADDATA,
		DDATAIN => DDATAIN,
		DDATAOUT => DDATAOUT,
		WE => WE,
		CE => CE,
		OE => OE,
		PIN => PIN,
		POUT => POUT,
		IR => IR,
		ERd => ERd,
		EPC => EPC,
		LDPC => LDPC,
		sPC => sPC,
		SUAL => SUAL
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
